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128 Commits

Author SHA1 Message Date
Richard Henderson
dd1ec408e5
target-*: Increment num_insns immediately after tcg_gen_insn_start 
This does tidy the icount test common to all targets.

Backports commit 959082fc4a93a016a6b697e1e0c2b373d8a3a373 from qemu
 2018-02-11 12:46:30 -05:00
Richard Henderson
a64d0ff657
target-*: Unconditionally emit tcg_gen_insn_start 
While we're at it, emit the opcode adjacent to where we currently
record data for search_pc. This puts gen_io_start et al on the
"correct" side of the marker.

Backports commit 667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 from qemu
 2018-02-11 12:41:20 -05:00
Lioncash
b3f9ff667b
tcg: Rename debug_insn_start to insn_start 
With an eye toward making it mandatory.

Backports commit 765b842adec4c5a359e69ca08785553599f71496 from qemu
 2018-02-11 12:34:01 -05:00
Richard Henderson
77b03e0973
target-i386: Make check_hw_breakpoints static 
The function is now only used from within a single file.

Backports commit dd941cdcfec536aad6a310a153778142ed9f3e92 from qemu
 2018-02-11 12:28:08 -05:00
Richard Henderson
10e0920fa0
target-i386: Move breakpoint related functions to new file 
Backports commit ba4b5c65a98ea91dc3b13e42dd9404808c999dda from qemu
 2018-02-11 12:25:24 -05:00
Richard Henderson
232632e76c
tcg: Change translator-side labels to a pointer 
This is improved type checking for the translators -- it's no longer
possible to accidentally swap arguments to the branch functions.

Note that the code generating backends still manipulate labels as int.

With notable exceptions, the scope of the change is just a few lines
for each target, so it's not worth building extra machinery to do this
change in per-target increments.

Backports commit 42a268c241183877192c376d03bd9b6d527407c7 from qemu
 2018-02-09 14:17:56 -05:00
Lioncash
0273e6ae18
tcg: Put opcodes in a linked list 
The previous setup required ops and args to be completely sequential,
and was error prone when it came to both iteration and optimization.
 2018-02-09 12:54:05 -05:00
Richard Henderson
a41b9acc0c
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full 
The method by which we count the number of ops emitted
is going to change. Abstract that away into some inlines.

Backports commit fe700adb3db5b028b504423b946d4ee5200a8f2f from qemu.
 2018-02-09 09:31:17 -05:00
Richard Henderson
78378289e3
tcg: Move emit of INDEX_op_end into gen_tb_end 
Backports commit 0a7df5da986bd7ee0789f2d7b8611f2e8eee5046 from qemu
 2018-02-09 08:51:01 -05:00
Richard Henderson
6b4b493dae
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr 
Thus, use cpu_env as the parameter, not TCG_AREG0 directly.
Update all uses in the translators.

Backports commit e1ccc05444676b92c63708096e36582be27fbee1 from qemu
 2018-02-08 12:33:33 -05:00
Nguyen Anh Quynh
3e0d0cfab7 i386: fix signed int overflow in #923 & #924 2017-12-16 10:28:45 +08:00
Andrew Dutcher
d7735487f7 Use the qemu helpers to get/set the x86 eflags (#878) 2017-09-15 22:18:38 +07:00
vardyh
ad767abda8 x86::trans: handle illegal case for opc c6/c7 
Reference Intel software developer manual vol2 Appendix A Table A-6 for
detailed decoding information.

Signed-off-by: vardyh <vardyh.dev@gmail.com>
 2017-05-25 15:22:45 +08:00
bulaza
4b9efdc986 Adding INSN hook checks for x86 (#833) 
* adding INSN hook checking for x86

* tabs to spaces

* need to return bool not uc_err

* fixed conditional after switching to bool
 2017-05-14 00:16:17 +07:00
Samuel Groß
5385baba39 Implemented read and write access to the YMM registers (#819) 2017-05-05 09:02:58 +08:00
Ryan Hileman
1b00d3f89a remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
Nguyen Anh Quynh
c01dcf0a14 fix merge conflicts 2017-03-10 21:04:33 +08:00
Ahmed Samy
02e6c14e12 x86: add MSR API via reg API (#755) 
Writing / reading to model specific registers should be as easy as
calling a function, it's a bit stupid to write shell code and run them
just to write/read to a MSR, and even worse, you need more than just a
shellcode to read...

So, add a special register ID called UC_X86_REG_MSR, which should be
passed to uc_reg_write()/uc_reg_read() as the register ID, and then a
data structure which is uc_x86_msr (12 bytes), as the value (always), where:
	Byte	Value		Size
	0	MSR ID		4
	4       MSR val		8
 2017-02-24 21:37:19 +08:00
Nguyen Anh Quynh
6ea39f7d5a merge msvc with master 2017-02-24 10:39:36 +08:00
Chris Eagle
a03e908611 Fix initial state of segment registers (#751) 
* Remove glib from samples makefile

* changes to 16 bit segment registers needs to update segment base as well as segment selector

* change how x86 segment registers are set in 16-bit mode

* more appropriate solution to initial state of x86 segment registers in 16-bit mode

* remove commented lines
 2017-02-09 23:49:54 +08:00
Chris Eagle
f05984961b Fix 16-bit address computations (#747) 
* Remove glib from samples makefile

* changes to 16 bit segment registers needs to update segment base as well as segment selector

* change how x86 segment registers are set in 16-bit mode
 2017-02-08 09:37:41 +08:00
Nguyen Anh Quynh
0680b85920 cleanup Monitor related code 2017-01-23 10:07:01 +08:00
Nguyen Anh Quynh
55d472c62c cleanup Monitor related code 2017-01-23 00:53:31 +08:00
xorstream
e46f86c80b Merging with current msvc. 2017-01-23 01:07:06 +11:00
xorstream
72a497bc14 Added MIPS support and projects for all samples. 2017-01-23 01:05:08 +11:00
Nguyen Anh Quynh
206819bd98 cleanup after msvc port 2017-01-22 21:27:17 +08:00
xorstream
770c5616e2 Automated leading tab to spaces conversion. 2017-01-21 12:28:22 +11:00
xorstream
df41c49e2d Fixed warning about {} initialisers. 2017-01-21 11:41:11 +11:00
xorstream
429bfca48e Fixes for MSVC native support to still work with GCC/GNU. 2017-01-21 01:07:10 +11:00
xorstream
fac6a66860 platform.h move #3 2017-01-21 00:13:21 +11:00
xorstream
b0ae2138fb Merge remote-tracking branch 'unicorn-engine/master' into msvc_native 2017-01-20 22:37:51 +11:00
Nguyen Anh Quynh
42771848d6 no more spinlock 2017-01-20 14:57:33 +08:00
xorstream
002151874a Unicorn interface working with test app in 32bit and 64bit builds. 2017-01-20 17:27:22 +11:00
xorstream
1aeaf5c40d This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
Nguyen Anh Quynh
7512ff57de more cleanup 2017-01-10 16:29:47 +08:00
Chris Eagle
fccbcfd4c2 revert to use of g_free to make future qemu integrations easier (#695) 
* revert to use of g_free to make future qemu integrations easier

* bracing
 2016-12-21 22:28:36 +08:00
Chris Eagle
e46545f722 remove glib dependency by provide compatible replacements 2016-12-18 14:56:58 -08:00
Nguyen Anh Quynh
e1b65a6edb cleanup unused code 2016-11-19 23:48:23 +08:00
Nguyen Anh Quynh
b7cdbe7a88 Merge branch 'feat/reg_save_restore' of https://github.com/rhelmot/unicorn into rhelmot-feat/reg_save_restore 2016-10-07 09:57:07 +08:00
Ryan Hileman
cb615fdba7 remove uc->cpus 2016-09-23 07:38:21 -07:00
Nguyen Anh Quynh
69d976375e Merge branch 'fix/self_modifying' of https://github.com/rhelmot/unicorn into rhelmot-fix/self_modifying 2016-08-30 21:20:22 +08:00
Nguyen Anh Quynh
89c9ea5f8f Merge branch 'fix/eflags' of https://github.com/rhelmot/unicorn into rhelmot-fix/eflags 2016-08-24 16:13:31 +08:00
Andrew Dutcher
0ef2b5fd71 New feature: registers can be bulk saved/restored in an opaque blob 2016-08-20 04:14:07 -07:00
Andrew Dutcher
3a1f231e8f eflags patch 2016-08-09 19:38:44 -07:00
Andrew Dutcher
97b10da133 Undo the disaster that was the patch to unicorn github issue #266 and fix it correctly. makes normal self-modifying code work. 2016-08-09 19:35:20 -07:00
Andrew Dutcher
4a8f52ae7f support xmm registers 2016-08-09 19:34:34 -07:00
Nguyen Anh Quynh
cc6cbc5cf7 Merge branch 'memleak' into m2 2016-04-18 12:48:13 +08:00
Nguyen Anh Quynh
721f17eb74 Merge branch 'batch_reg' of https://github.com/lunixbochs/unicorn into lunixbochs-batch_reg 2016-04-06 09:39:22 +08:00
Nguyen Anh Quynh
70da2485fc x86: comment out restore_eflags() because it breaks some executions. see #505 2016-04-06 09:36:06 +08:00
Ryan Hileman
acd88856e1 add batched reg access 2016-04-04 20:51:38 -07:00